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NLSX4014 4-Bit 100 Mb/s Configurable Dual-Supply Level Translator
The NLSX4014 is a 4-bit configurable dual-supply bidirectional level translator without a direction control pin. The I/O VCC- and I/O VL-ports are designed to track two different power supply rails, VCC and VL respectively. The VCC supply rail is configurable from 1.3 V to 4.5 V while the VL supply rail is configurable from 0.9 V to (VCC - 0.4) V. This allows lower voltage logic signals on the VL side to be translated into higher voltage logic signals on the VCC side, and vice-versa. Both I/O ports are auto-sensing; thus, no direction pin is required. The Output Enable (EN) input, when Low, disables both I/O ports by putting them in 3-state. This significantly reduces the supply currents from both VCC and VL. The EN signal is designed to track VL.
Features http://onsemi.com MARKING DIAGRAMS
UQFN12 MU SUFFIX CASE 523AE WAMG G
1
WA = Specific Device Code M = Date Code G = Pb-Free Package (Note: Microdot may be in either location) 14 14 1 SOIC-14 D SUFFIX CASE 751A 1 14 14 1 TSSOP-14 DT SUFFIX CASE 948G 1 NLSX 4014 ALYWG G NLSX4014G AWLYWW
* Wide High-Side VCC Operating Range: 1.3 V to 4.5 V * * * * * * *
Wide Low-Side VL Operating Range: 0.9 V to (VCC - 0.4) V Power Supply Isolation All Outputs are in the High Impedance State if Either VL or VCC is at Ground High-Speed with 100 Mb/s Guaranteed Date Rate for VL > 1.6 V Low Bit-to-Bit Skew Overvoltage Tolerant Enable and I/O Pins Non-preferential Powerup Sequencing Small packaging: 1.7 mm x 2.0 mm UQFN12 These are Pb-Free Devices
Typical Applications
A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
* Mobile Phones, PDAs, Other Portable Devices
ORDERING INFORMATION
Device NLSX4014MUTAG NLSX4014DR2G NLSX4014DTR2G Package Shipping UQFN12 3000/T ape & Reel (Pb-Free) SO-14 2500/T ape & Reel (Pb-Free) TSSOP14 2500/T ape & Reel (Pb-Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2009
December, 2009 - Rev. 3
1
Publication Order Number: NLSX4014/D
NLSX4014
VL EN VL I/O VL1 I/O VL2 I/O VL3 I/O VL4
1 2 3 4 5 6 12 11 10 9 8 7
1 2 3 4 5 6 7
14 13 12 11 10 9 8
EN VCC I/O VCC1 I/O VCC2 I/O VCC3 NC I/O VCC4
VCC I/O VCC1 I/O VCC2 I/O VCC3 I/O VCC4
I/O VL1 I/O VL2 I/O VL3 I/O VL4 NC GND
GND (Top View)
Figure 1. Pin Assignments
EN VL VCC GND
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
I/O VL3
I/O VCC3
I/O VL4
I/O VCC4
Figure 2. Logic Diagram PIN ASSIGNMENT
Pins VCC VL GND EN I/O VCCn I/O VLn Description VCC Input Voltage VL Input Voltage Ground Output Enable I/O Port, Referenced to VCC I/O Port, Referenced to VL
FUNCTION TABLE
EN L H Operating Mode Hi-Z I/O Buses Connected
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NLSX4014
VL +1.8V +3.6V P One-Shot 4 kW VCC
VL +1.8 V System
NLSX4014
VCC +3.6 V System I/O VL N One-Shot I/O VCC
I/O1 I/On GND EN
I/O VL1
I/O VCC1
I/O1 I/On GND
I/O VLn I/O VCCn EN GND
P One-Shot 4 kW N One-Shot
Figure 3. Typical Application Circuit
Figure 4. Simplified Functional Diagram (1 I/O Line) (EN = 1)
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NLSX4014
MAXIMUM RATINGS
Symbol VCC VL I/O VCC I/O VL VEN IIK IOK ICC IL IGND TSTG VCC Supply Voltage VL Supply Voltage VCC-Referenced DC Input/Output Voltage VL-Referenced DC Input/Output Voltage Enable Control Pin DC Input Voltage Input Diode Clamp Current Output Diode Clamp Current DC Supply Current Through VCC DC Supply Current Through VL DC Ground Current Through Ground Pin Storage Temperature Parameter Value -0.5 to +5.5 -0.5 to +5.5 -0.5 to (VCC + 0.3) -0.5 to (VL + 0.3) -0.5 to +5.5 -50 -50 $100 $100 $100 -65 to +150 VI < GND VO < GND Condition Unit V V V V V mA mA mA mA mA C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VL VEN VIO TA DI/DV VCC Supply Voltage VL Supply Voltage Enable Control Pin Voltage Bus Input/Output Voltage Operating Temperature Range Input Transition Rise or Rate VI, VIO from 30% to 70% of VCC; VCC = 3.3 V $ 0.3 V I/O VCC I/O VL Parameter Min 1.3 0.9 GND GND GND -40 0 Max 4.5 VCC - 0.4 4.5 4.5 4.5 +85 10 Unit V V V V C ns
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NLSX4014
DC ELECTRICAL CHARACTERISTICS
-405C to +855C Symbol VIHC VILC VIHL VILL VIH VIL VOHC VOLC VOHL VOLL Parameter I/O VCC Input HIGH Voltage I/O VCC Input LOW Voltage I/O VL Input HIGH Voltage I/O VL Input LOW Voltage Control Pin Input HIGH Voltage Control Pin Input LOW Voltage I/O VCC Output HIGH Voltage I/O VCC Output LOW Voltage I/O VL Output HIGH Voltage I/O VL Output LOW Voltage TA = +25C TA = +25C I/O VCC Source Current = 20 mA I/O VCC Sink Current = 20 mA I/O VL Source Current = 20 mA I/O VL Sink Current = 20 mA Test Conditions (Note 1) VCC (V) (Note 2) 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 VL (V) (Note 3) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) Min 0.8 * VCC - 0.8 * VL - 0.8 * VL - 0.8 * VCC - 0.8 * VL - Typ (Note 4) - - - - - - - - - - Max - 0.2 * VCC - 0.2 * VL - 0.2 * VL - 0.2 * VCC - 0.2 * VL Unit V V V V V V V V V V
1. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified. 2. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions. 3. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC - 0.4) V during normal operation. However, during startup and shutdown conditions, VL can be greater than (VCC - 0.4) V. 4. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25C. All units are production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design.
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NLSX4014
POWER CONSUMPTION
Symbol IQ-VCC Parameter Test Conditions (Note 5) VCC (V) (Note 6) VL (V) (Note 7) -405C to +855C Min -
-
Typ - - - -
Max 1.0 2.0 2.0 1.0
Unit mA
Supply Current from EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V, 1.3 to 3.6 0.9 to (VCC - 0.4) VCC I/O VCCn = VCC or I/O VLn = VL and Io = 0 0 4.1 4.5 0
- -
IQ-VL
Supply Current from EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V, 1.3 to 3.6 0.9 to (VCC - 0.4) VL I/O VCCn = VCC or I/O VLn = VL and Io = 0 EN = VL, I/O VCCn = 0 V, I/O VLn = 0 V, I/O VCCn = VCC or I/O VLn = (VCC - 0.2 V) and Io = 0 < (VCC - 0.2) 0 4.5 4.1 0
mA
-
-
2.0
ITS-VCC
VCC Tristate Output Mode Supply Current VL Tristate Output Mode Supply Current I/O Tristate Output Mode Leakage Current Output Enable Pin Input Current VL Port VCC Port
EN = 0 V
1.3 to 3.6 0.9 to (VCC - 0.4)
-
-
1.0
mA
ITS-VL
EN = 0 V EN = 0 V EN = 0 V EN = 0 V - I/O VLn = 0 to 4.1 V I/O VCCn = 0 to 4.5 V
1.3 to 3.6 0.9 to (VCC - 0.4) VCC - 0.2 1.3 to 3.6 0.9 to (VCC - 0.4) VCC - 0.2 1.3 to 3.6 0.9 to (VCC - 0.4) 0 to 4.5 0 0 0 to 4.1
- - - - - - -
- - - - - - -
0.2 2.0 0.15 2.0 1.0 2.0 2.0
mA
IOZ
mA
IEN IOFF
mA mA
5. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified. 6. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 3.6 V. 7. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC - 0.4) V during normal operation. However, during startup and shutdown conditions, VL can be greater than (VCC - 0.4) V.
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NLSX4014
TIMING CHARACTERISTICS
-405C to +855C Symbol tR-VCC tF-VCC tR-VL tF-VL ZO-VCC ZO-VL Parameter I/O VCC Rise Time (Output = I/O_VCC) I/O VCC Falltime (Output = I/O_VCC) I/O VL Risetime (Output = I/O_VL) I/O VL Falltime (Output = I/O_VL) I/O VCC One-Shot Output Impedance I/O VL One-Shot Output Impedance CIOVCC = 15 pF Test Conditions (Note 8) CIOVCC = 15 pF CIOVCC = 15 pF CIOVL = 15 pF CIOVL = 15 pF VCC (V) (Note 9) 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 VL (V) (Note 10) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) Min Typ (Note 11) 0.7 0.5 1.0 0.6 30 30 4.5 9.3 Max 2.4 1.0 3.8 1.2 Unit ns ns ns ns W W ns
tPD_VL-VCC Propagation Delay (Output = I/O_VCC, tPHL, tPLH) tPD_VCC-VL Propagation Delay (Output = I/O_VL, tPHL, tPLH) tSK VL-VCC Channel-to-Channel Skew (Output = I/O_VCC)
CIOVL = 15 pF
1.3 to 4.5
0.9 to (VCC - 0.4)
3.0
6.5
ns
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC - 0.4)
0.2
0.3
nS
tSK_VCC-VL Channel-to-Channel Skew (Output = I/O_VL) MDR Maximum Data Rate
CIOVCC = 15 pF
1.3 to 4.5
0.9 to (VCC - 0.4)
0.2
0.3
nS
(Output = I/O_VCC, CIOVCC = 15 pF) (Output = I/O_VL, CIOVL = 15 pF)
1.3 to 4.5 > 2.2
0.9 to (VCC - 0.4) > 1.8
110 140
Mb/s
8. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified. 9. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions. 10. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC - 0.4) V during normal operation. However, during startup and shutdown conditions, VL can be greater than (VCC - 0.4) V. 11. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25C. All units are production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design.
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NLSX4014
ENABLE / DISABLE TIME MEASUREMENTS
-405C to +855C Symbol tEN-VCC Parameter Turn-On Enable Time (Output = I/O_VCC, tpZH) Turn-On Enable Time (Output = I/O_VCC, tpZL) tEN-VL Turn-On Enable Time (Output = I/O_VL, tpZH) Turn-On Enable Time (Output = I/O_VL, tpZL) tDIS-VCC Turn-Off Disable Time (Output = I/O_VCC, tpHZ) Propagation Delay (Output = I/O_VCC, tPLZ) tDIS-VL Turn-Off Disable Time (Output = I/O_VL, tpHZ) Propagation Delay (Output = I/O_VL, tPLZ) Test Conditions (Note 12) CIOVCC = 15 pF CIOVL = 15 pF CIOVCC = 15 pF CIOVL = 15 pF CIOVCC = 15 pF CIOVL = 15 pF CIOVCC = 15 pF CIOVL = 15 pF VCC (V) (Note 13) 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 1.3 to 4.5 VL (V) (Note 14) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) 0.9 to (VCC - 0.4) Min Typ (Note 15) 130 100 95 70 175 150 180 160 Max 180 150 185 110 250 190 250 220 Unit ns ns ns ns ns ns ns ns
12. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified. 13. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions. 14. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC - 0.4) V during normal operation. However, during startup and shutdown conditions, VL can be greater than (VCC - 0.4) V. 15. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25 C. All units are production tested at TA = +25 C. Limits over the operating temperature range are guaranteed by design. NLSX4014 EN Source I/O VL I/O VCC CIOVCC I/O VL CIOVL Source I/O VL 90% 50% 10% tPD_VL-VCC I/O VCC 90% 50% 10% tF-VCC tR-VCC tRISE/FALL v 3 ns I/O VCC 90% 50% 10% tPD_VL-VCC tPD_VCC-VL I/O VL 90% 50% 10% tF-VL tR-VL tPD_VCC-VL tRISE/FALL v 3 ns NLSX4014 EN I/O VCC
VL
VCC
VL
VCC
Figure 5. Driving I/O VL Test Circuit and Timing
Figure 6. Driving I/O VCC Test Circuit and Timing
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NLSX4014
VCC R1 CL RL 2xVCC OPEN
PULSE GENERATOR RT
DUT
Test tPZH, tPHZ tPZL, tPLZ
Switch Open 2 x VCC
CL = 15 pF or equivalent (Includes jig and probe capacitance) RL = R1 = 50 kW or equivalent RT = ZOUT of pulse generator (typically 50 W)
Figure 7. Test Circuit for Enable/Disable Time Measurement
tR Input tPLH Output 90% 50% 10% 90% 50% 10% tR tPHL tF 50% VL GND HIGH IMPEDANCE 10% 90% VOL VOH HIGH IMPEDANCE
VCC GND
EN
tPZL Output 50% tPZH Output 50%
tPLZ
tF
tPHZ
Figure 8. Timing Definitions for Propagation Delays and Enable/Disable Measurement
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NLSX4014
IMPORTANT APPLICATIONS INFORMATION
Level Translator Architecture Uni-Directional versus Bi-Directional Translation
The NLSX4014 auto sense translator provides bi-directional voltage level shifting to transfer data in multiple supply voltage systems. This device has two supply voltages, VL and VCC, which set the logic levels on the input and output sides of the translator. When used to transfer data from the VL to the VCC ports, input signals referenced to the VL supply are translated to output signals with a logic level matched to VCC. In a similar manner, the VCC to VL translation shifts input signals with a logic level compatible to VCC to an output signal matched to VL. The NLSX4014 consists of four bi-directional channels that independently determine the direction of the data flow without requiring a directional pin. The one-shot circuits are used to detect the rising or falling input signals. In addition, the one shots decrease the rise and fall time of the output signal for high-to-low and low-to-high transitions.
Input Driver Requirements
The NLSX4014 can function as a non-inverting uni-directional translator. One advantage of using the translator as a uni-directional device is that each I/O pin can be configured as either an input or output. The configurable input or output feature is especially useful in applications such as SPI that use multiple uni-directional I/O lines to send data to and from a device. The flexible I/O port of the auto sense translator simplifies the trace connections on the PCB.
Power Supply Guidelines
For proper operation, the input driver to the auto sense translator should be capable of driving 2.0 mA of peak output current.
Output Load Requirements
The NLSX4014 is designed to drive CMOS inputs. Resistive pullup or pulldown loads of less than 50 kW should not be used with this device. The NLSX3373 or NLSX3378 open-drain auto sense translators are alternate translator options for an application such as the I2C bus that requires pullup resistors.
Enable Input (EN)
The NLSX4014 has an Enable pin (EN) that provides tri-state operation at the I/O pins. Driving the Enable pin to a low logic level minimizes the power consumption of the device and drives the I/O VCC and I/O VL pins to a high impedance state. Normal translation operation occurs when the EN pin is equal to a logic high signal. The EN pin is referenced to the VL supply and has Over-Voltage Tolerant (OVT) protection.
It is recommended that the VL supply should be less than or equal to the value of the VCC minus 0.4 V. The sequencing of the power supplies will not damage the device during the power up operation; however, the current consumption of the device will increase if VL exceeds VCC minus 0.4 V. In addition, the I/O VCC and I/O VL pins are in the high impedance state if either supply voltage is equal to 0 V. For optimal performance, 0.01 to 0.1 mF decoupling capacitors should be used on the VL and VCC power supply pins. Ceramic capacitors are a good design choice to filter and bypass any noise signals on the power supply voltage lines to the ground plane of the PCB. The noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the PCB connection traces. The NLSX4014 provides power supply isolation if either supply voltage VL or VCC is equal to 0 V. The isolation occurs because the I/O pins are in the high impedance state. It is recommended that pulldown resistors should be used if the VL or VCC are floated or in a high impedance state. A pulldown resistor connected from the supply voltage to ground ensures that the translator's supply voltage is equal to 0 V.
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NLSX4014
PACKAGE DIMENSIONS
UQFN12 1.7x2.0, 0.4P CASE 523AE-01 ISSUE A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. MOLD FLASH ALLOWED ON TERMINALS ALONG EDGE OF PACKAGE. FLASH 0.03 MAX ON BOTTOM SURFACE OF TERMINALS. 5. DETAIL A SHOWS OPTIONAL CONSTRUCTION FOR TERMINALS. DIM A A1 A3 b D E e K L L1 L2 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 1.70 BSC 2.00 BSC 0.40 BSC 0.20 ---0.45 0.55 0.00 0.03 0.15 REF
D
AB L1
2X 2X
0.10 C 0.10 C
0.05 C
12X
0.05 C A3
8X
K
5 7
DETAIL A
1 12X
L L2
BOTTOM VIEW
II II
TOP VIEW A A1 SIDE VIEW e
11
PIN 1 REFERENCE
E
DETAIL A
NOTE 5
DETAIL B OPTIONAL CONSTRUCTION
DETAIL B
C
SEATING PLANE
MOUNTING FOOTPRINT SOLDERMASK DEFINED
2.00
12X
b 0.10 0.05
M M
CAB C
NOTE 3
1 0.32 2.30
11X
0.40 PITCH
0.22
12X
0.69
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NLSX4014
PACKAGE DIMENSIONS
SOIC-14 D SUFFIX CASE 751A-03 ISSUE J
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G
C
R X 45 _
F
DIM A B C D F G J K M P R
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT
7X
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
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NLSX4014
PACKAGE DIMENSIONS
TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE B
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 --- 1.20 --- 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
DIM A B C D F G H J J1 K K1 L M
SOLDERING FOOTPRINT
7.06 1
0.36
14X
14X
1.26
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III III III III
0.65 PITCH
DIMENSIONS: MILLIMETERS
NLSX4014/D

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